1. Field of the Invention
The present invention relates to internal voltage generation circuits and particularly to a configuration of a circuit for generating a boosted voltage used in a dynamic random access memory.
2. Description of the Background Art
A dynamic random access memory (DRAM), widely used as main memory, is formed mainly through a CMOS (complementary metal-insulating film-semiconductor) process. The DRAM has a memory cell configured of a capacitor and a single access transistor. This access transistor is generally formed of an n-channel MOS transistor having a larger charge driving capability than a p-channel MOS transistor (an insulated gate field effect transistor).
To store data of a high level in this memory cell capacitor, a boosted voltage Vpp higher than a normal voltage corresponding to high level data is applied to a gate of the access transistor, with its threshold voltage loss considered. Typically, the DRAM is internally provided with a booster circuit (a Vpp generation circuit) for obtaining boosted voltage Vpp from an external power supply voltage ExVdd supplied from an outside of the chip (DRAM). Incorporating the Vpp generation circuit reduces current consumption due to dispensable charging and discharging a line transmitting the boosted voltage, and simplifies a system power supply arrangement, as compared to a configuration of externally generating boosted voltage Vpp and supplying boosted voltage Vpp to a DRAM.
FIG. 24 shows an example of a configuration of a conventional Vpp generation circuit. In FIG. 24, the Vpp generation circuit includes a rectifying element (a diode) D1 connected between an external power supply node ND1 and a node ND2, a rectifying element D2 connected between node ND2 and an output node ND3, and a capacitance element C1 supplying electric charge to node ND2 in response to a pump clock signal xcfx86. Rectifying element D1 has an anode connected to external power supply node ND1 and a cathode connected to node ND2. Rectifying element D2 has an anode connected to node ND2 and a cathode connected to node ND3. Pump clock signal xcfx86 has a predetermined period and a predetermined amplitude.
When pump clock signal xcfx86 is at a low level, rectifying element D1 conducts and node ND2 is precharged to a voltage level of ExVddxe2x88x92Vth. Herein, Vth represents a forward voltage drop of rectifying elements D1 and D2. When pump clock signal xcfx86 rises to a high level, node ND2 has its voltage level increased by an amplitude Vcc of pump clock signal xcfx86. More specifically, the voltage level of node ND2 increases to a voltage level of Vcc +ExVddxe2x88x92Vth. Rectifying element D2 conducts as the voltage level of node ND2 increases, and rectifying element D2 supplies electric charge to node ND3 and increases boosted voltage Vpp in voltage level. By repeating this operation, boosted voltage Vpp rises to at most a voltage level of ExVdd+Vccxe2x88x922xc2x7Vth. If pump clock signal xcfx86 has an amplitude equal to external power supply voltage ExVdd, boosted voltage Vpp accordingly rises to a voltage level of 2xc2x7ExVddxe2x88x922xc2x7Vth.
In the Vpp generation circuit as shown in FIG. 24, capacitance element C1 has an charge supplying capability substantially proportional to the capacitance value of capacitance element C1, since Q=Cxc2x7V.
FIG. 25 schematically shows a configuration of a portion generating boosted voltage Vpp in a conventional DRAM. In FIG. 25, an active Vpp generation circuit 902 and a standby Vpp generation circuit 904 are provided for a DRAM circuit 906. Active Vpp generation circuit 902 is activated in an active cycle of DRAM circuit 906 (when a memory cell select operation is performed) to generate boosted voltage Vpp. Standby Vpp generation circuit 904 normally operates and compensates for a reduction of boosted voltage Vpp caused by a leak current when DRAM circuit 906 is in a standby state. Therefore, standby Vpp generation circuit 904 is adapted to have a small current driving capability and active Vpp generation circuit 902 is adapted to have a large current driving capability. For example, boosted voltage Vpp is used not only for a word line drive signal but also for bit line isolation instructing signal in a shared sense amplifier configuration. Boosted voltage Vpp is also used for a bit line equalization instructing signal for equalizing bit lines, to rapidly precharge/equalize the bit lines.
In the active cycle, the bit line isolation and equalization instructing signals are charged and discharged (the signals are discharged when the active cycle starts and the signals are charged when the active cycle is completed) and further boosted voltage Vpp is consumed in selecting a word line. Therefore, in the active cycle, active Vpp generation circuit 902 having a large current driving capability is activated and generates boosted voltage Vpp with the large current driving capability reliably.
Typically, a DRAM has a plurality of modes of operation, and, as has been described previously, a Vpp generation circuit is required to have different current supplying capabilities for different modes of operation and the DRAM has a specification value of power consumption that varies in correspondence to the mode of operation. In a standby cycle, minimizing power consumption is required. Therefore, active Vpp generation circuit 902 having a large current supplying capability and a large power consumption and standby Vpp generation circuit 904 having a small current supplying capability and a small power consumption are used to supply DRAM circuit 906 with boosted voltage Vpp. Active Vpp generation circuit 902 and standby Vpp generation circuit 904 are selectively activated depending on a mode of operation of the DRAM circuit to satisfy a current supplying capability of a Vpp generation circuit and a specification value for power consumption of the DRAM.
Active Vpp generation circuit 902 and standby Vpp generation circuit 904 both utilize the charge pump circuit as shown in FIG. 24. If boosted voltage Vpp is generated by a charge pump circuit and boosted voltage Vpp has a voltage level dropping due to leak current or consumption thereof, boosted voltage Vpp varies in a saw-tooth form. More specifically, as shown in FIG. 26, when pump clock signal xcfx86 goes high, node ND2 has a voltage level increased from a precharge voltage level by an amplitude of pump clock signal xcfx86. In response to the increase of the voltage level, rectifying element D2 conducts and supplies electric charge to node ND3. In response to the supply of electric charge, boosted voltage Vpp has a voltage level increasing rapidly.
If boosted voltage Vpp drops in level because of consumption of boosted voltage Vpp through an operation of an internal circuit or because of a leak current through a leak path, node ND2 has a voltage level gradually lowered since electric charge is applied from node ND2 to node ND3 when pump clock signal xcfx86 is held high. When pump clock signal xcfx86 falls low, node ND2 has a voltage level once dropped and again rectifying element D1 allows node ND2 to return to the precharge voltage level. When pump clock signal xcfx86 is held low, rectifying element D2 does not conduct and boosted voltage Vpp continues to lower. This operation is repeated and boosted voltage Vpp has a saw-tooth like voltage waveform. In particular, in active Vpp generation circuit 902, capacitance element C1 has a capacitance value sufficiently increased to accommodate a large current consumption in the active cycle, and a large amount of electric charge is transferred to node ND2 and electric charge is rapidly supplied from node ND2 via rectifying element D2 to node ND3. Thus, the saw-tooth waveform becomes large in amplitude.
A circuit configuration employing a multi-phase clock signal to provide a charge pump operation, as shown in FIG. 27, to minimize the variation of boosted voltage Vpp can be used.
FIG. 27 schematically shows another configuration of the conventional Vpp generation circuit. In FIG. 27, the Vpp generation circuit includes rectifying elements D3 and D4 connected in series between an external power supply node ND1 and an output node ND3, rectifying elements D5 and D6 connected in parallel with rectifying elements D3 and D4 and in series between external power supply node ND1 and output node ND3, a capacitance element C2 performing a pump operation in response to a pump clock signal xcfx861 to supply electric charge to a node ND4 located between rectifying elements D3 and D4, and a capacitance element C3 supplying electric charge in response to a pump clock signal xcfx862 to a node ND5 located between rectifying elements D5 and D6. Capacitance elements C2 and C3 have a capacitance value C/2 corresponding to xc2xd of capacitance value C of the capacitance element in the circuit as shown in FIG. 24 using a single-phase pump clock signal. Further, pump clock signals xcfx861 and xcfx862 are two-phase clock signals complementary to each other. Now, an operation of the Vpp generation circuit as shown in FIG. 27 will be described with reference to the signal waveform diagram as shown in FIG. 28.
When pump clock signal xcfx861 has a high level, pump clock signal xcfx862 is at a low level. Therefore, when node ND4 has a voltage level increasing in response to pump clock signal xcfx861 and electric charge is supplied via rectifying element D4 to node ND3, node ND5 drops in voltage level and rectifying element D3 does not conduct. Thus, node ND3 receives electric charge in proportion to capacitance value C/2 of capacitance element C2 and boosted voltage Vpp at output node ND3 increases in level. This level of boosted voltage Vpp gradually drops due to consumption or leak current. When pump clock signal xcfx861 is held high, node ND4 receives electric charge from capacitance element C2, although node ND4 gradually drops in voltage level as output node ND3 drops in voltage level.
When pump clock signal xcfx861 falls low, pump clock signal xcfx862 goes high. Therefore, when a charge supply operation via rectifying element D4 is completed, electric charge is then supplied via rectifying element D6. Herein, capacitance element C3 has a capacitance value of C/2 equal to capacitance value C/2 of capacitance element C2 and boosted voltage Vpp is boosted with a boosting width reduced to correspond to xc2xd of an amplitude provided when a single-phase pump clock signal as shown in FIG. 24 is used. Therefore, if a two-phase clock signal is used as shown in FIG. 28, then boosted voltage Vpp has a saw-tooth waveform having half the amplitude of the saw-tooth waveform as shown in FIG. 26. Thus, boosted voltage Vpp can have a voltage level with a reduced variation. If a clock signal having more phases, such as a 4-phase clock signal, is used, boosted voltage Vpp can have a voltage level further reduced in variation.
In recent years, there has been provided, as one application of a DRAM, a system LSI having a large-scale logic circuit and a DRAM of a relatively small storage capacity integratedly mounted on a single semiconductor chip. Hereinafter a DRAM used for such an application will be referred to as an embedded DRAM. In such an application, the DRAM is required to have various storage capacities depending on a target application. In particular, if it is applied to portable equipment or the like, the DRAM is required to operate with low power supply voltage. Therefore, various requirements on specifications for a power supply voltage externally supplied to the DRAM are presented in some cases. Depending on the specification of interest, an operating power supply voltage required for a Vpp generation circuit varies, and depending on the application of interest, the DRAM is required to have a different storage capacity. Specifications for the charge supplying capability and current consumption and the like of the Vpp generation circuit vary accordingly
With the assumption of such various specifications, if a Vpp generation circuit has a fixed configuration as shown in FIG. 25, then for an application to the DRAM requiring a small storage capacity there would exist a Vpp generation circuit having a capability larger than required and thus occupying an area larger than required. If a multi-phase pump clock signal is used and charge pump circuits are arranged for respective pump clock signals having different phases, the charge pump circuitry would have too large a pump driving capability for a DRAM of a small storage capacity. Therefore, the charge pump circuit needs to be redesign depending on the application or specification of interest, deteriorating the design efficiency.
FIG. 29 schematically shows another configuration of the Vpp generation circuitry. As shown in FIG. 29, the Vpp generation circuitry includes an active Vpp generation circuit 902 and a standby Vpp generation circuit 904 and a Vpp assisting/directly coupling circuit 908 provided at a different location. Vpp assisting/directly coupling circuit 908 includes an initial charge assisting circuit for rapidly driving boosted voltage Vpp to a predetermined voltage level upon power-on, and an external direct-coupling circuit for estimating or testing internal circuit (DRAM circuit) 906 even when boosted voltage Vpp is defective. The external direct-coupling circuit couples an external power supply node with a boosted voltage transmission line. Therefore, the initial charge assisting circuit is required to have a current driving capability matching with a current driving capability of Vpp generation circuits 902 and 904, and the external direct-coupling circuit is also required to have a current capability matching with the current driving capability of Vpp generation circuits 902 and 904. Therefore, if the DRAM has a changed specification and Vpp generation circuits 902 and 904 are accordingly have a changed specification, then a Vpp assisting/directly coupling circuit 908 is accordingly also required to be redesigned.
Therefore, if a conventional DRAM is subject to change in specification of storage capacity and in operating power supply voltage, an internal voltage generation circuit such as a Vpp generation circuit needs to be redesigned. Therefore it cannot flexibly accommodate a changed specification, disadvantageously resulting in an increased cost and an increased designing period.
An object of the present invention is to provide an internal voltage generation circuit capable of readily generating an internal voltage such as a boosted voltage, which is capable of readily accommodating a change in a specification.
Another object of the present invention is to provide an internal voltage generation circuit suitable for an embedded DRAM used for various applications.
Briefly state, an internal voltage generation circuit according to the present invention has a plurality of pump modules arranged therein, with the number of pump modules to be activated being adjusted depending on the charge supplying capability required.
More specifically, an internal voltage generation circuit according to the present invention includes a plurality of pump modules each performing a pump operation when active, to commonly generate an internal voltage on an internal voltage transmission line, and control circuitry coupled with the plurality of pump modules to generate a control signal for activating a pump module and transmit the generated control signal to the pump module. The control circuitry includes a circuit for setting the number of pump modules to be activated among the plurality of pump modules.
A plurality of pump modules are arranged and the number of pump modules to be simultaneously activated can be adjusted depending on the specification required. Therefore, if a change is made in a specification, such specification change can be accommodated simply by changing the number of pump modules to be activated. Therefore, it is not necessary to change the design of the entirety of the internal voltage generation circuit. Thus, the change in the specification can be readily accommodated.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.